Conventional erasable programmable read only memory (EPROM) cells are floating gate transistors having a control gate, floating gate, and a channel between a source and a drain. EPROM cells are programmed by inducing a current across a channel then pulling hot electrons up to a floating gate by application of a positive voltage to a control gate and are erased by application of ultraviolet light. Various techniques using Fowler-Nordheim tunneling have been implemented for erasing such cells in order to obtain electrically erasable programmable read only memory (EEPROM) cells. Such an EEPROM cell typically has a select transistor in series with a floating gate transistor. The select transistor is necessary for addressing the EEPROM cell. Programming is achieved by inducing a current through the floating gate transistor then pulling hot electrons into the floating gate with the same technique as with EPROM cells. Erasing, which requires drawing the electrons out of the floating gate, has been achieved in two different ways. One approach is to apply an erase signal, a positive voltage, to the control gate of the floating gate transistor of sufficient strength to draw the electrons out of the floating gate to the control gate. The disadvantage of this approach is that an oxide layer between the floating gate and the channel must be relatively thin and the voltage applied to the control gate must be relatively large. Another approach has been to extend the floating gate to an area which is in proximity to a special conductor, distinct from the control gate of the floating gate transistor, so that application of an erase signal to the special conductor can draw the electrons from the floating gate through an erase window formed between the special conductor and the floating gate. The advantage of this approach is that the oxide layer between channel and floating gate need not be as thin and the erase signal need not be as high in voltage as in the first approach. Also, the erase window can be altered as to size, dielectric constant, and voltage required to induce tunneling. Because cells developed from the second approach require a special conductor for the erase signal, memory circuits having an array of such cells require an extra conductor for each row. The increased complexity is, of course, a disadvantage. A cell of the prior art which uses the second approach is described by Burkhard Geibel, "An 8 K EEPROM Using the SIMOS Storage Cell," IEEE Journal of Solid State Circuits, Vol. SC-15, No. 3, pp. 311-314.